1. Field of the Invention
The present invention relates to a semiconductor device manufacturing method and, more particularly, a method of manufacturing a semiconductor device having a capacitor.
2. Description of the Prior Art
As the nonvolatile memory that can still store the information after the power supply is turned OFF, the flash memory and the ferroelectric memory (FeRAM) are well known.
The flash memory has the floating gate that is buried in the gate insulating film of the insulated-gate field effect transistor (IGFET), and stores the information by accumulating charges as the stored information into the floating gate. The tunnel current must be supplied to the gate insulating film to write/erase the information, and thus the relatively high voltage is required.
The FeRAM has the ferroelectric capacitor that stores the information by utilizing the hysteresis characteristic of the ferroelectric substance. The ferroelectric film, which is formed between the upper electrode and the lower electrode in the ferroelectric capacitor, generates the polarization in reply to the voltage value applied between the upper electrode and the lower electrode, and has the spontaneous polarization that holds the polarization after the applied voltage is removed. If the polarity of the applied voltage is inverted, the polarity of the spontaneous polarization is also inverted. The information can be read by sensing the polarization and the magnitude of this spontaneous,polarization.
The FeRAM has such a merit that it can operate at a lower voltage than the flash memory and thus the high-speed writing can be executed in a power saving mode.
The memory cell of the FeRAM has a structure shown in FIG. 1 and FIG. 2, for example. FIG. 1 is a plan view showing a part of the memory cell area of the FeRAM, wherein insulating layers other than an element isolation insulating layer are omitted from illustration. FIG. 2 is a sectional view taken along a I—I line in FIG. 1.
In FIG. 1, a well region 103 that is surrounded with an element isolation insulating layer 102 is formed on a silicon substrate 101. Then, MOS transistors 107a, 107b having sectional structures, as shown in FIG. 2, are formed in the well region 103. Then, planar capacitors 100 having sectional structures, as shown in FIG. 2, are formed on the obliquely upper of the well region 103.
In FIG. 2, two gate electrodes 105a, 105b are formed over the well region 103, which is surrounded with the element isolation insulating layer 102, of the silicon substrate 101 via a gate insulating film 104. Also, impurity diffusion regions 106a, 106b, 106c each having the LDD structure are formed in the well region 103 on both sides of respective gate electrodes 105a, 105b. The first MOS transistor 107a consists of one gate electrode 105a, the impurity diffusion regions 106a, 106b, etc. Also, the second MOS transistor 107b consists of the other gate electrode 105b, the impurity diffusion regions 106b, 106c, etc.
The element isolation insulating layer 102 and the MOS transistors 107a, 107b are covered with first and second insulating layers 108, 109. The first insulating layer 108 is made of the material that functions as an oxidation preventing layer. An upper surface of the second insulating layer 109 is planarized by the chemical mechanical polishing (CMP) method. The ferroelectric capacitor 100 is formed on the upper surface of the second insulating layer 109.
The ferroelectric capacitor 100 has a lower electrode 100a having a contact region, a ferroelectric layer 100b, and an upper electrode 100c. Also, a third insulating layer 110 is formed on the capacitor 100 and the second insulating layer 109. The lower electrode 100a is formed by patterning a platinum layer. Also, the ferroelectric layer 100b is formed by patterning a PZT layer, for example. Also, the upper electrode 100c is formed by patterning an iridium oxide layer, for example.
The ferroelectric capacitor 100, the third insulating layer 110, and the contact region of the lower electrode 100a are covered with a capacitor-protection insulating film 113 made of aluminum oxide.
First and second contact holes 110a, 110c are formed in the first to third insulating layers 108 to 110 on the impurity diffusion regions 106a, 106c located near both ends of the well region 103 respectively. A third contact hole 110b is formed in the first to third insulating layers 108 to 110 on the impurity diffusion region 106b located between two gate electrodes 104a, 104b. Also, as shown in FIG. 1, a fourth contact hole 110d is formed in the third insulating layer 110 on the contact region that is located near the end of the lower electrode 100a and is not covered with the ferroelectric layer 100b. 
First to fourth conductive plugs 111a to 111d each made of an adhesive conductive layer and a tungsten layer are formed in the first to fourth contact holes 110a to 110d. Also, a fifth contact hole 112 is formed on the upper electrode 100c of the capacitor 100.
A first wiring 120a, which is connected to an upper surface of the first conductive plug 111a and also connected to the upper electrode 100c via the fifth contact hole 112, is formed on the third insulating layer 110. Also, a second wiring 120c, which is connected to an upper surface of the second conductive plug 111c and also connected to another upper electrode 100c via another fifth contact hole 112, is formed on the third insulating layer 110. Also, a conductive pad 120b is formed on the third insulating layer 110 and the third conductive plug 111b. Also, a third wiring 120d, which is connected to the fourth conductive plug 111d located on the contact region of the lower electrode 100a, is formed on the third insulating layer 110.
In the meanwhile, as the third insulating layer 110 formed on the capacitor 100 and the second insulating layer 109, normally a silicon oxide layer formed by the plasma CVD method using TEOS as the material is employed. Such insulating layer is also set forth in Patent Application Publication (KOKAI) 2001-60669, for example.
However, the insulating layer that is formed by using TEOS as the material causes the end deterioration of the ferroelectric capacitor. The end deterioration signifies such phenomenon that the capacitors, which are located at the end portion of the lower electrode 100 a and located in vicinity of the contact region not covered with the dielectric layer 100b, of a plurality of capacitors 100 shown in FIG. 1 are ready to deteriorate.
As the method of preventing the characteristic deterioration of the capacitor, it is set forth in Patent Application Publication (KOKAI) Hei 11-330390 that the insulating film that has the tensile stress on the ferroelectric capacitor should be formed on the capacitor. However, merely the improvement in the characteristics of one capacitor is set forth in this reference, but description is not made of the prevention of the end deterioration caused in a plurality of capacitors that are formed to use commonly one stripe-like lower electrode respectively. In addition, it is not set forth in this reference which method should be employed to improve the characteristics of a plurality of capacitors uniformly with regard to the prevention of the end deterioration.